As the technology node for semiconductor devices continues to shrink, for example to 20 nm and below, various schemes are being investigated to replace the nickel platinum silicide scheme currently used at up to the 20 nm node. Many of the new schemes under investigation require the use of many separate fabrication tools for the realization of the contacting scheme. However, the inventors have observed that the use of separate process chambers each configured to perform one or more processes (e.g., layer deposition, etching, annealing, or the like) required for the fabrication of the completed device can lead to undesired exposure of the device to an uncontrolled environment outside of the process chambers. Such exposure may contaminate the device or cause unintended reactions with portions of the device (e.g., oxidation of layers), thereby adversely affecting the characteristics of the completed device.
Therefore, the inventors have provided an improved integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices.